Network controller with tri-core architecture

The netX 10 has a tri-core architecture with a central 32-bit/100-MHz ARM CPU, a 32-bit/100-MHz RISC controller as communication system for all field-buses or as an Ethernet port and a further

32-bit/100-MHz RISC controller for fast signal processing. It functions as a compact single chip solution in automated devices with network connection, such as O/Is, drives, sensors or ID systems. The protocol execution controller xPEC is adapted by replacing the microcode on the determining processing of the status machine protocol and the communication functions of the respective network.

In contrast to this, the peripheral interface controller xPIC can be freely programmed by the user and  allows a fast signal processing parallel to the ARM-CPU, e.g., as motion or PLC core with Codesys or as intelligent IO-link controller. The xPIC can access the entire address space of the netX 10 and with its second register base achieves an interrupt latency time of only 50 ns on external signals. The command set includes all standard  RISC instructions, expanded by a 32x32-bit multiplication, fast loop logic and saturation support, which is all carried out in one cycle. All processor cores are connected via a central data switch with the internal RAM, the memory controller and the two peripheral buses. The general peripheral units, such as GPIO, timer, interrupt controller, UART, USB, SPI, I²C and the AD converter, encoder,

PWMs for signals and outputs are distributed on these. The memory bus guided from this can be configured as a dual port memory for connection to a host CPU, as memory controller for SRAM and SDRAM or as simple PIOs. The SPI mode of the DPMs enables a fast serial access to the internal memory.

The program code is loaded via the SPI interface in the internal SRAM and in SQI mode enables an 'execution in place' of the program code directly from the serial Flash Eprom. A Cordic unit is implemented for fast calculation of transcendent functions (some exponential functions, logarithms, sine and cosine).

With xPIC and the separate peripheral bus an independent IO or motion function block can be installed. All function units can be synchronized with each other.

24 signals can be selected from the periphery block via the internal multiplexer and reducing the BGA housing to 13 mm × 13 mm with 197 connections. The netX 10 is specified for the expanded temperature range and has guaranteed delivery for ten years.

Using the standardized JTAG and ETM interface (embedded trace macrocell) all market available ARM development tools can be connected. Based on Eclipse, there is a complete development environment with C compiler and comfortable operating of the internal debug unit with single step and break points via USB available.